DIGITAL DESIGN WITH QUARTUS WORKSHOP - PowerPoint PPT Presentation

About This Presentation
Title:

DIGITAL DESIGN WITH QUARTUS WORKSHOP

Description:

DIGITAL DESIGN WITH QUARTUS WORKSHOP by Dr. Junaid Ahmed Zubairi Dept of Computer Science SUNY at Fredonia, Fredonia NY Workshop Outline Introduction to the workshop ... – PowerPoint PPT presentation

Number of Views:7
Avg rating:3.0/5.0
Slides: 39
Provided by: DonTo8
Learn more at: http://cs.fredonia.edu
Category:

less

Transcript and Presenter's Notes

Title: DIGITAL DESIGN WITH QUARTUS WORKSHOP


1
DIGITAL DESIGN WITH QUARTUS WORKSHOP
  • by
  • Dr. Junaid Ahmed Zubairi
  • Dept of Computer Science
  • SUNY at Fredonia, Fredonia NY

2
Workshop Outline
  • Introduction to the workshop and setting targets
  • Combinational and sequential logic
  • Quartus-II package features and usage guide
  • Hands on VHDL (Lab1)
  • VHDL design units
  • Designing a simple circuit and its testing (Lab2)
  • Design of a sequential logic circuit (lab3)
  • Design project

3
Introduction and Setting Targets
  • This workshop is about using VHDL for VLSI design
  • Participants are expected to learn a subset of
    VHDL features using Altera Quartus-II platform

4
What is VHDL?
  • VHDL is VHSIC (Very High Speed Integrated
    Circuits) Hardware Description Language
  • VHDL is designed to describe the behavior of the
    digital systems
  • It is a design entry language
  • VHDL is concurrent
  • Using VHDL test benches, we can verify our design
  • VHDL integrates nicely with low level design
    tools

5
Why VHDL?
  • It is IEEE standard (1076 and 1164)
  • VHDL includes VITAL (IEEE 1076.4), using which
    the timing information can be annotated to a
    simulation model
  • VHDL has hierarchical design units
  • Learning VHDL and Verilog is easy mastering is
    difficult
  • VHDL and Verilog are identical in functionality

6
VHDL Within VLSI Design Cycle
  • VLSI design starts with (not always!!) capturing
    an idea on the back of an envelope
  • From the specifications, one needs to construct a
    behavioral description of the circuit
  • When one describes how information flows between
    registers in a design, it is called RTL (register
    transfer level)

7
VHDL Within VLSI Design Cycle
  • A structure level description defines the circuit
    in terms of a collection of components
  • VHDL supports behavioral, RTL and structural
    descriptions, thus supporting various levels of
    abstraction
  • Most VHDL users prefer RTL descriptions and use
    VHDL as input to the synthesis process
  • Synthesis tools then optimize and compile the
    design as per specified constraints and map to
    target devices as per libraries

8
VHDL Within VLSI Design Cycle
  • Gate level simulation is conducted to verify the
    design using the same test vectors that were
    generated for RTL simulation
  • Finally the place and route tools are used for
    layout generation and timing closure

9
PLD Design Flow
Design Specification
Design Entry/RTL Coding - Behavioral or
Structural Description of Design
RTL Simulation - Functional Simulation
(Modelsim, Quartus II) - Verify Logic Model
Data Flow (No Timing Delays)
M512
LE
Synthesis - Translate Design into Device
Specific Primitives - Optimization to Meet
Required Area Performance Constraints -
Precision, Synplify, Quartus II
M4K
I/O
Place Route - Map Primitives to Specific
Locations inside Target Technology with
Reference to Area Performance Constraints
- Specify Routing Resources to Be Used
10
PLD Design Flow
Timing Analysis - Verify Performance
Specifications Were Met - Static Timing Analysis
tclk
Gate Level Simulation - Timing Simulation -
Verify Design Will Work in Target Technology
PC Board Simulation Test - Simulate Board
Design - Program Test Device on Board - Use
SignalTap II for Debugging
11
Quartus-II Software
  • We will be using Quartus-II software by Altera
  • This package allows us to write and compile VHDL
    designs and perform RTL simulation with waveforms
  • Please download Quartus-II from www.altera.com if
    not installed already
  • Install the license by requesting 30-days grace
    period. After the expiry of the 30-days period,
    You can redirect the license to the
    redwood.cs.fredonia.edu server. We have three
    floating licenses set up for full version.

12
Quartus II Development System
  • Fully-Integrated Design Tool
  • Multiple Design Entry Methods
  • Logic Synthesis
  • Place Route
  • Simulation
  • Timing Power Analysis
  • Device Programming

13
More Features
  • MegaWizard SOPC Builder Design Tools
  • LogicLock Optimization Tool
  • NativeLink 3rd-Party EDA Tool Integration
  • Integrated Embedded Software Development
  • SignalTap II SignalProbe Debug Tools
  • Windows, Solaris, HPUX, Linux Support
  • Node-Locked Network Licensing Options
  • Revision Control Interface

14
Quartus II Operating Environment
15
Main Toolbar Modes
Dynamic menus
Compiler Report
Floorplans
Execution Controls
Window new file buttons
To Reset Views Tools ?ToolbarsgtReset
All Restart Quartus II
16
Exercise-PreLab1 Feel the Menus
  • Launch the Quartus-II software and identify the
    main menu item that leads to the following
    choices
  • New Project Wizard
  • Compilation icon and menu item
  • Generate Functional Simulation Netlist
  • Start Simulation item and icon
  • License Setup
  • Open recent files and projects
  • Launch a new file

17
Lab-1
  • Lab-1 is a short and simple project designed to
    get you started in shortest possible time
  • Lab-1 handout will be distributed separately
  • Lab-1 calls for designing a half-adder in VHDL
    and simulating it in Quartus-II

18
VHDL Syntax
  • You may use UPPERCASE for reserved words in VHDL
    and lowercase words for your chosen names but it
    is not necessary
  • The basic building blocks of VHDL design are
    ENTITY declaration and ARCHITECTURE body
  • The VHDL file name must be the same as the ENTITY
    name

19
VHDL Syntax
  • ENTITY declaration treats the design as a black
    box. It just names the inputs and outputs as
    ports
  • It does not specify how the circuit works
  • The last entry in the port declaration is not
    followed by a semicolon
  • Each signal has a signal mode (IN, OUT or BUFFER)
    and a signal type (BIT, BIT_VECTOR, STD_LOGIC,
    STD_LOGIC_VECTOR)

20
VHDL Syntax
  • Std_logic and std_logic_vector are part of IEEE
    library. They allow additional values -(dont
    care), Z (hi-Z) and X (indeterminate)
  • In order to use IEEE values, you should use the
    following statements
  • library ieee
  • use ieee.std_logic_1164.all

21
Architecture
  • The functional relation between the input and
    output signals is described by the architecture
    body
  • Only one architecture body should be bound to an
    entity, although many architecture bodies can be
    defined
  • Architecture body can be written in many
    different ways

22
Data Flow Style
  • We have used the concurrent assignment statements
    in Lab-1 code
  • sumltA xor B
  • carrylt A and B
  • The concurrent assignment takes place based on
    the activity on RHS of the arrow

23
Structural Style
  • We can also describe the architecture based on a
    list of components used and mapping of our
    circuits signals to the inputs and outputs of
    the components
  • Usually it is done to build a circuit that uses
    several independent design units

24
Using Components
  • Begin with the design of bottom units in VHDL
  • Save each unit in a separate VHDL file declaring
    it as a new project in Quartus-II
  • Design the top unit next as a new project,
    placing bottom units in the VHDL file as
    components
  • Name the project as the top unit , include the
    bottom unit files in the project and then compile
  • Next lab places half adders as components in a
    full adder

25
Lab-2
  • Lab-2 uses two half adders to build a full adder
    as shown in the next slide
  • It is important to define the internal connectors
    as signal variables in VHDL code
  • Signals will connect the two half adders as
    shown.
  • All signals must be named and defined in the
    architecture body

26
Lab 2 Full Adder Design
27
Lab 3
  • library ieee
  • use ieee.std_logic_1164.all
  •  
  • entity adderfour is
  • port (Cinin std_logic
  • xin std_logic_vector(3 downto 0)
  • yin std_logic_vector(3 downto 0)
  • sout std_logic_vector(3 downto 0)
  • Coutout std_logic)
  • end adderfour

28
Lab 3
  • architecture compo of adderfour is
  • signal c1,c2,c3std_logic
  • component full_adder
  • port (X,Y,Cinin std_logic
  • sum,Coutout std_logic)
  • end component
  • begin
  • stage0full_adder port map (Cin,x(0),y(0),s(0),c1)
  • stage1full_adder port map (c1,
    x(1),y(1),s(1),c2)
  • stage2full_adder port map (c2,x(2),y(2),s(2),c3)
  • stage3full_adder port map (c3,x(3),y(3),s(3),Cout
    )
  • end compo

29
Components
  • The source code shown builds a four-bit ripple
    carry adder
  • It uses four 1-bit full adders as components
  • The structural style is just like specifying a
    network with all its inputs, outputs and
    intermediate wires
  • All intermediate wires are declared in the
    architecture body as signals

30
Using Vectors
  • Instead of naming each wire separately, we group
    them together and give them a common name
  • For example, in a 4-bit adder, we use four inputs
    x3,x2,x1,x0
  • We can also declare a vector called X.
  • X in std_logic_vector(3 downto 0)
  • X(3), X(2), X(1), X(0) can be referred
    individually

31
Lab 4 Design of a Simple Circuit
  • Using VHDL, design a simple 4-bit 2-function
    combo box that accepts two four bit numbers (A,B)
    and produces the complement of A if a control
    input C is 0 otherwise it sets the output to
    the result of logical AND (A AND B). Test your
    circuit with one set of different inputs and one
    set of identical inputs. For example 1011 and
    1001, 0110

32
Clock Signal
  • Synchronous Sequential circuits require the use
    of a clock signal. Clock signal can be generated
    easily in VHDL
  • As an example, look at the following code
    segment
  • Clk lt not(Clk) after 10ns
  • The Clk wire is assigned its opposite value after
    10ns.
  • In Quartus, you generate clock waveform by
    editing the .vwf file. Select clk input and use
    Overwrite Clock option

33
Sequential Logic
  • Design of an edge triggered D flip flop
  • (Demo)
  • Adding asynchronous reset to the flip flop
  • (Demo)
  • How do you convert it to latch?

34
Sequential (VHDL code)
  • library ieee
  • use ieee.std_logic_1164.all
  • entity my_ff is
  • port (D,clk,resetin std_logic Qout std_logic)
  • end my_ff

35
Sequential (VHDL code)
  • architecture synch of my_ff is
  • begin
  • process (clk,reset)
  • begin
  • if reset'1' then
  • Q lt'0'
  • elsif clk'1' and clk'EVENT then
  • QltD
  • end if
  • end process
  • end synch

36
Explanation
  • The source code shown implements a D flip flop
    that is rising edge triggered and uses
    asynchronous reset
  • The rising edge is detected by the following
    statement
  • elsif clk'1' and clk'EVENT then QltD
  • This statement says that if clk has a current
    value of 1 and if there has been an event on the
    clk line, assign Q the value of D
  • Asynchronous reset is achieved by first checking
    if reset has a value 1

37
Behavior Modeling With Process
  • In the D flip flop design, we have introduced the
    3rd type of architecture body, i.e. sequential
    flow
  • Sequential execution is implemented in VHDL with
    process() statement.
  • A process consists of a sensitivity list and a
    series of statements to be executed in the order
    in which they are written
  • The process is called as soon as the value of any
    one member of the sensitivity list is changed

38
Lab 5
  • Build 8-bit parallel load register by using eight
    D flip flops as components
  • Demonstrate its working by simulation
Write a Comment
User Comments (0)
About PowerShow.com