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## Lecture 2: Hardware Modeling with Verilog HDL

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Title: Lecture 2: Hardware Modeling with Verilog HDL

1
Lecture 2 Hardware Modeling with Verilog HDL
2
Verilog HDL Hardware Modeling
• Hardware Encapsulation Verilog Module
• Module Ports
• Module Implementation
• Hardware Modeling Verilog Primitives
• Descriptive Styles
• Explicit Structural Description
• Implicit Structural Description Continuous
Assignments
• Structural Connections
• Behavioral Descriptions in Verilog
• Hierarchical Descriptions of Hardware
• Structural (Top-Down) Design Methodology
• Arrays of Instances
• Using Verilog for Synthesis

3
Verilog Module Example
module Add_half (sum, c_out, a, b) input a,
b output sum, c_out wire c_out_bar xor (sum,
a, b) nand (c_out_bar, a, b) not (c_out,
c_out_bar) endmodule
This is an explicit structural description of a
4
module Add_half_2 (sum, c_out, a, b) input a,
b output c_out, sum assign (c_out, sum) a
b endmodule
Continuous assignment statement is used. This is
an implicit structural description of a half
adder The synthesis tools need to create an
optimal gate-level realization
5
Instantiation of Modules
module Add_full (sum, c_out, a, b, c_in) input
a, b, c_in output c_out, sum wire w1, w2,
(sum, w3, w1, c_in) or (c_out, w2,
w3) endmodule Here we instantiate Add_half
twice. i.e., placing two Add_half circuits and
connecting them. This full adder is built from
two half adders and an OR gate.
6
Verilog Primitives
• Verilog primitives implement pre-defined
hardware-based behavior.
• Built-in primitives
• User-Defined Primitives (UDP)
• All pre-defined primitives are combinational.
• The output of a combinational primitive must be
of type net.
• The inputs of a primitive can be of type net or
reg
• Verilog supports combinational and sequential
UDP.

7
Four-Valued Logic
• Verilog Logic Values
• The underlying data representation allows for any
bit to have one of four values
• 1, 0, x (unknown), z (high impedance)
• x one of 1, 0, z, or in the state of change
• z the high impedance output of a tri-state
gate.
• What basis do these have in reality?
• 0, 1 no question
• z A tri-state gate drives either a zero or one
on its output. If its not doing that, its
output is high impedance (z). Tri-state gates
are real devices and z is a real electrical
affect.
• x not a real value. There is no real gate that
drives an x on to a wire. x is used as a
debugging aid. x means the simulator cant
determine the answer and so maybe you should
worry!

8
Four-Valued Logic
• Logic with multi-level logic values
• Logic with these four values make sense
• Nand anything with a 0, and you get a 1. This
includes having an x or z on the other input.
Thats the nature of the nand gate
• Nand two xs and you get an x
• Note z treated as an x on input. Their rows and
columns are the same
• If you forget to connect an input it will be
seen as an z.
• At the start of simulation, everything is an x.

9
Delay
• Specify gate delay
• nand 1 G1(y1, a1, b1), G2(y2, a2, b2), G3(y3,
a3, b3)
• Specify rising delay, falling delay
• specify
• specparam
• Tpd_0_1 1.133.097.75 //min delaytypical
delaymax delay
• Tpd_1_0 0.932.507.34 //min delaytypical
delaymax delay

10
Model Propagation Delay Example
• module nandf201 (O, A1, B1)
• input A1, B1
• output O
• nand (O, A1, B1)
• specify
• specparam
• Tpd_0_1 1.133.097.75,
• Tpd_1_0 0.932.507.34
• (A1 gt O) (Tpd_0_1, Tpd_1_0)
• (B1 gt O) (Tpd_0_1, Tpd_1_0)
• endspecify
• endmodule

ASIC cell library module of a nand gate
11
Verilog Model Descriptive Styles
• Explicit Structural Description
• another example using silicon foundry cell
library
• module Add_half_structural (sum, c_out, a, b)
• output sum, c_out
• input a, b
• wire c_bar
• xorf201 G1 (sum, a, b)
• nanf201 G2 (c_bar, a, b)
• invf101 G3 (c_out, c_bar)
• endmodule
• Implicit Structural Description Continuous
Assignments

12
Implicit Structural Model Example
• module bit_or (y, a, b)
• input 70 a, b // declare a, b 8-bit wide
• output 70 y
• assign y a I b //bitwise or
• endmodule
• // another example
• module adder (sum, a, b)
• parameter width 7
• input width0 a, b
• output width0 sum
• assign sum a b
• endmodule

13
Module Port Connections
• module parent_mod
• wire 30 g
• child_mod G1 (g3, g1, g0, g2) // listed
order is significant
• endmodule
• module child_mod (sig_a, sig_b, sig_c, sig_d)
• input sig_a, sig_b
• output sig_c, sig_d
• // child_mod design is here
• endmodule

14
Behavior Model in Verilog
• The basic essence of a behavioral model is the
process.
• The process can be thought of as an independent
• The process can be implemented as a sequential
state machine, as a microcoded controller, as an
asynchronous clearing of a register, or as a
combinational logic circuit.
• The key idea is that we conceive the behavior of
digital systems as a set of these independent,
but communicating processes.
• The actual implementation is left to the context
of the description (what level of abstraction we
are dealing with) and the time and area
constraints of the implementation.

15
Behavior Models in Verilog HDL
• Statements used in behavioral modeling
• always, initial, if-then-else, loops
• module m16 (value, clock)
• output 30 value
• reg 30 value
• input clock
• always _at_(posedge clock)
• value value 1
• endmodule

16
Behavioral Models in Verilog HDL
• another example
• module m555 (clock)
• output clock
• reg clock
• initial
• 5 clock 1
• always
• 50 clock clock
• endmodule

17
Behavioral Model DFF
module DFF(q, d, clock) output q input d,
clock reg q always _at_ (posedge clock)
module DFF(q, d, clock) output q input d,
clock reg q always _at_ (posedge clock) 5
q d endmodule
18
Behavioral Model nand gate
• module beharioralNand (out, in1, in2, in3)
• output out
• input in1, in2, in3
• reg out
• parameter delay 5
• always _at_ (in1 or in2 or in3)
• delay out (in1 in2 in3)
• endmodule

19
A DFF with synchronous set and rest
• module Flip_flop (q, data_in, clk, set, rst)
• input data_in, set, rst, clk
• output q
• reg q
• always _at_ (posedge clk)
• begin
• if (rst 0) q 0 // rst is active low
• else
• if (set 0) q 1 // set is active low
• else
• q data_in
• end
• endmodule

20
Hierarchical Descriptions of HW
• design a 1-bit ALU
• design a 32-bit ALU by cascading 32 1-bit ALUs
• many design examples

21
Arrays of Instances
• module array_of_nor (y, a, b)
• input 70 a, b
• output 70 y
• nor 70 (y, a, b)
• endmodule
• module array_of_flops (q, data_in, clk, set,
rst)
• input 70 data_in
• input clk, set, rst
• output 70 q
• Flip_flop M70 (q, data_in, clk, set, rst)
• endmodule

22
A FSM Example in Verilog HDL
module fsm (out, in, clock, reset) output
out input in, clock, reset reg out reg 10
currentState, nextState always _at_(in or
currentState) begin // the combinational
portion out currentState1
currentState0 nextState 0 if
(currentState 0) if (in) nextState 1 if
(currentState 1)
23
A FSM Example in Verilog HDL (cont.)
if (in) nextState 3 if (currentState
3) if (in) nextState 3 else nextState
1 end always _at_(posedge clock or negedge
reset) begin // the sequential portion if
(reset) currentState lt 0 else currentState
lt nextState end endmodule
What is the state transition diagram of this FSM?
24
Non blocking Assignment lt
• The non-blocking assignment is used to
synchronize assignment statements so that they
all appear to happen at once concurrently
• The non-blocking assignment is used with an edge.
• When the specified edge occurs, then the new
values are loaded concurrently in all assignments
waiting for the edge.
• The regular assignment updates its left-hand
side immediately
• an example
• _at_(posedge clock)
• m 3
• n 75
• n lt m
• r n
• // Question What value is assigned to r?